Injector Design for Optimized Tunneling in Standard CMOS Floating-Gate Analog Memories
نویسندگان
چکیده
Programming mechanisms in floating-gate non-volatile (EEPROM) standard-CMOS memories are briefly reviewed. A methodology to optimize the programming time in poly1-poly2 Fowler-Nordheim based structures is proposed. From design constraints, the optimum number of bumps and bootstrap capacitance value are obtained to maximize the programming speed for a given programming voltage.
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